A small computer system, such as a business machine, usually has a central processor unit, a terminal (for input), a printer (for output), and one or more peripheral data storage units such as a disk. In general business use, to avoid accidental loss of important current operating data, it is important to provide backup for the storage. For this purpose, most business users routinely, such as once a day, copy the storage contents onto a removable medium and put it away for safekeeping.
With the recent availability of the small Winchester (fixed) disk, designers of small business computer systems have wanted to move to this disk as the principal data storage medium for the system. Winchester disks are cheaper, faster, more reliable, and have more capacity than previously used disks. However, since the Winchester is a fixed disk, it is not removable from the system. Therefore, removable backup storage must be provided.
One solution is to combine an 8-inch Winchester fixed disk with an 8-inch floppy disk. This floppy disk can be used for backup, and removed for safekeeping; it is convenient to store.
A control unit or interface is generally provided between the central processor and data storage means of small computer systems. The control unit, generally incorporating a microprocessor, performs managerial functions connected with reading and writing the disk, and frees the central processor from responsibility for such tasks. When a single data storage means is used, the controller can be designed to be suitable to that storage means and to operate it efficiently.
However, when two data storage means of different characteristics, such as a fixed disk and a floppy disk, are to be controlled together, a different problem arises. To provide two separately operating controllers, each dedicated to its particular disk, is obviously both cumbersome and expensive. It would therefore be desirable to provide a single controller between the central processor and both disks, employing at least some common circuitry. A single controller would require fewer chips than would two interfaces, and would therefore be less expensive.
However, the differences between the two kinds of disk are so great as to make the design of a common controller a difficult matter. A fixed Winchester disk and a floppy backup disk transfer data signals at quite different rates. A fixed Winchester disk has a transfer rate of from three to eight million bytes per second; a dual-sided double-density floppy disk has a transfer rate of 500 kilobytes per second; and a single density floppy disk has a transfer rate of 250 kilobytes per second. Fixed and floppy disks also require different controller architectures to perform different read, write and format operations; additional differences are entailed if there is a need to provide both single-density and double-density capabilities for the floppy disk.
If all the operations appropriate to each disk are separately provided for, by providing dedicated circuitry, the controller will be expensive. There will also be more opportunities for components to fail. It is therefore desirable to provide for operation of the different disks and modes of operation with as much common circuitry as possible. On the other hand, if a single microprocessor is employed, programmed to provide the various modes of operation, the limitation of the speed of execution of the program will severely limit the speed capability of the controller. Such a controller will be unable to operate some of the fastest disks. In addition, the complexity of programming required will in practice limit the number of peripheral storage means that can be controlled by a single controller using a programmed microprocessor.
Moreover, it may be desirable to change the particular disks or other data storage means employed with a particular data processing system and controller, and it is obviously desirable to provide a controller that is flexible enough to be used with other data storage means, and that is easily adapted to be so used. If large amounts of dedicated circuitry must be changed to accommodate new data storage means, it will be a difficult task to adapt the controller. On the other hand, it will also be very difficult to adapt a controller employing a programmed microprocessor, because the program is complex and rewriting it is a time-consuming task.
An example of a prior art controller intended to control a Winchester fixed disk and a floppy disk is the "DSD 880", made by Data Systems Design, Inc., and described in an article in the September 1980 issue of the magazine Mini Micro Systems, published by Cahners Publishing Co.
This controller employs a programmed bit-slice microprocessor, However, this controller is designed to control two peripheral data storage units, a fixed and a floppy disk, and to modify it to control additional units would be very difficult. Any such modification would add greatly to the complexity of the program, so that in practice this controller is limited to two or three controlled devices. Similarly, to change one of the controlled devices to another type of device would also call for major reprogramming and would be a difficult adaptation. The top speed of the controller is limited by the rate at which the microprocessor can execute its instructions, which is in practice very close to the speed of current fixed disks. Any future disk having a somewhat increased rate of data transfer would not be usable with this controller.
It is therefore an object of this invention to provide a single device that can interface between the central processor of a data processing system and a plurality of data storage means having different data transfer rates and different control operations.
It is also an object of the invention to provide such a controller that is capable of controlling data storage means having extremely fast data transfer.
It is a further object of the invention to provide such a single device that is quickly and easily adaptable to interface to a different plurality of data storage means, or to data storage means having different modes of operation.
It is another object of the invention to provide such a device that uses a minimum of circuit elements, and is therefore economical to manufacture, and simple and reliable in operation.
According to the invention, an improved controller is provided in a data processing system of the kind having a central processing unit and a plurality of peripheral data storage units. Each peripheral data storage unit transfers data signals at a characteristic rate, and the rates are distinct. The central processing unit provides and receives data signals, and provides control signals including data storage unit select, read, write and format control signals.
The controller is connected between the central processing unit and the peripheral data storage units. The controller provides temporary data storage, and is adapted to transfer data signals between the central processing unit and the temporary storage, and between the temporary storage and any of the peripheral data storage units, responsive to the central processing unit control signals.
The controller provides the same number of instruction storage units as there are peripheral data storage units. The controller further provides selection and addressing means connected to the instruction storage units, and a single instruction register, each of the instruction storage units being connected to the instruction register. The controller provides controller timing means, which is responsive to the characteristic data signal transfer rate of a selected peripheral data storage unit to provide controller timing signals corresponding to its transfer rate. The controller selection and addressing means is responsive to the data storage unit select control signal to select one of the instruction storage units, is further responsive to one of the read, write and format control signals to provide initial address signals addressing an initial instruction in said selected instruction storage unit, and is further responsive to the controller timing signals to increment the initial address to provide successively incremented address signals.
The instruction register is responsive to the controller timing signals to be loaded with signals representing the initially addressed instruction of the selected instruction storage unit, and successively with signals representing instructions addressed by the incremented address signals.
The controller further provides common data storage unit operating circuitry connected to the peripheral data storage units, which is responsive to signals output from the instruction register to transfer data signals between a selected peripheral data storage unit and the controller temporary storage as controlled by the central processing unit control signals.
Preferably, the instruction register provides a write mode signal and a read mode signal. The common operating circuitry is responsive to the write mode signal to send data signals to the selected peripheral data storage unit, and responsive to the read mode signal to receive data signals from the selected peripheral data storage unit. The controller timing means comprises means responsive to data signals received from a selected peripheral data storage unit to provide a read mode timing signal, means responsive to the data storage unit select signals to provide a write mode timing signal, and timing signal select means providing a controller timing signal corresponding to the characteristic data transfer rate of a selected peripheral data storage unit. The timing signal select means is responsive to the read mode signal and to the read mode timing signal to provide the read mode timing signal as the controller timing signal, and is responsive to the write mode signal and to the write mode timing signal to provide the write mode timing signal as the controller timing signal.
Each instruction storage unit contains all instructions necessary for the operating circuitry to operate the corresponding peripheral storage unit. The instructions in each portion (read, write or format) of an instruction storage unit are sequentially executable beginning with the initial instruction. The instruction storage units are adapted for easy removal or replacement, so that the controller is adaptable to be connected to a variable plurality of peripheral data storage units by varying the set of instruction storage units.